Semiconductor device and a method for manufacturing the same

ABSTRACT

Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/350,117, filed Feb. 9, 2006 and which application claims priorityfrom Japanese patent application No. 2005-032976 filed on Feb. 9, 2005,the contents of which are hereby incorporated by reference into thisapplication.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and amanufacturing technology thereof, particularly to a semiconductor devicehaving a nonvolatile memory such as EEPROM (Electrically ErasableProgrammable Read Only Memory) or a flash memory and a technologyeffective when applied to its manufacturing method.

For example, a semiconductor integrated circuit device having a thirdgate, which has a function different from that of a floating gate and acontrol gate, buried in a space between floating gates existing in adirection vertical or parallel to a word line (control gate) andchannel, and a manufacturing method of the device are described inJapanese Unexamined Patent Publication No. 2001-28428.

In Japanese Unexamined Patent Publication No. 2004-152977, described isa semiconductor memory device having an assist gate electrode at aposition which is between source and drain regions formed in parallel toeach other and is parallel to these regions but does not overlaptherewith, using the assist electrode as an assist electrode forsource-side hot electron injection during writing and an inversion layerformed below the assist electrode as the source or drain region duringreading.

SUMMARY OF THE INVENTION

AND flash memories having assist gate (AG) electrodes (which willhereinafter be called “AG-AND flash memories”) which carry out writingoperations by source-side hot electron injection have been developed. Byusing assist gate electrodes as writing gates to drastically decrease achannel current, writing in memory cells of a kilo-bit class can becarried out simultaneously in a short period of time. In addition, thearea of memory cells can be reduced by employing a self alignmentprocess for the formation of floating gate electrodes and employingassist gate electrodes for field isolation.

AG-AND flash memories having floating gate electrodes manufactured in aself alignment process can be formed, for example, in the followingmanner. First, assist gate electrodes are formed over the main surfaceof a semiconductor substrate and sidewalls made of an insulating filmare formed on the side surfaces of each of the assist gate electrodes.After formation of a tunnel insulating film (FTO (Fowler-Nordheim TunnelOxide) film) over the surface of the semiconductor substrate exposedbetween two adjacent assist gate electrodes, each floating gateelectrode is formed between two adjacent assist gate electrodes. Thesidewalls are formed by depositing an insulating film covering therewiththe assist gate electrodes, and then subjecting the film to anisotropicdry etching using, for example, RIE (Reaction Ion Etching) to leave theinsulating film only on the side surfaces of the assist gate electrodes.Control gate electrodes are then formed over the floating gateelectrodes via an interlayer film.

AG-AND flash memories having floating gate electrodes formed by a selfalignment process have, however, various technical problems which willbe described below.

It has been elucidated that when sidewalls are formed over the sidesurfaces of each of the assist gate electrodes, anisotropic dry etchinggives a damage to the surface of the semiconductor substrate and thisdamage causes a reduction in breakdown voltage of the tunnel insulatingfilm which will be formed by the later step. The present inventorsinvestigated removal of a damage layer by etching, after the anisotropicdry etching, the surface of the semiconductor substrate by about 10 nmby post-treatment (dry etching) and then forming a pre-oxide film overthe surface of the semiconductor substrate by thermal oxidation.Addition of the post-treatment and thermal oxidation steps howevercomplicates the manufacturing process. Moreover, an etched amount of thesemiconductor substrate during the post-treatment varies largely, whichcauses a reduction in the breakdown voltage of the tunnel insulatingfilm owing to partial thinning of the tunnel insulating film. This leadsto deterioration in repeated rewriting characteristics of the memorycell.

An object of the present invention is to provide a technology capable ofimproving the reliability of a semiconductor device having a flashmemory.

The above-described and the other objects and novel features of thepresent invention will be apparent from the description herein andaccompanying drawings.

Of the inventions disclosed by the present application, therepresentative ones will next be summarized briefly.

In the present invention, there is thus provided a semiconductor devicehaving, over a semiconductor substrate, a plurality of nonvolatilememory cells each comprising a plurality of assist gate electrodes, aplurality of control gate electrodes placed to intersect with theplurality of assist gate electrodes, and a plurality of floating gateelectrodes for charge accumulation disposed at a position which isbetween any two adjacent ones of the plurality of assist gate electrodesand two-dimensionally overlaps with the plurality of control gateelectrodes, wherein the lower surface of the plurality of floating gateelectrodes lies at a higher position than the lower surface of theplurality of assist gate electrodes.

In the present invention, there is also provided a manufacturing methodof a semiconductor device, which comprises the steps of forming aplurality of layered patterns obtained by stacking over a semiconductorsubstrate, a tunnel insulating film, and a conductor film and aninsulating film for the formation of floating gate electrodes in theorder of mention, forming sidewalls over the side surfaces of each ofthe plurality of layered patterns, removing a damage layer of thesemiconductor substrate between any two adjacent ones of the pluralityof layered patterns by dry etching, forming an assist gate insulatingfilm over the semiconductor substrate between any two adjacent ones ofthe plurality of layered patterns, and forming a plurality of assistgate electrodes over the assist gate insulating film between any twoadjacent ones of the plurality of layered patterns in self alignmentwith the plurality of layered patterns.

An advantage of the representative inventions, of the inventionsdisclosed by the present application, will next be described briefly.

The present invention makes it possible to form a tunnel insulating filmof a memory cell over the main surface of a semiconductor substratewhich is clean and damage-free so that the memory cell thus obtained hashigh reliability, resulting in improvement of the reliability of thesemiconductor device having a flash memory.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a fragmentary plan view of an AG-AND flash memory according toEmbodiment 1 of the present invention;

FIG. 2 is a cross-sectional view taken along a line a-a of FIG. 1;

FIG. 3 is a cross-sectional view taken along a line b-b of FIG. 1;

FIG. 4 is a fragmentary cross-sectional view of the AG-AND flash memoryof Embodiment 1 of the present invention during its manufacturing step;

FIG. 5 is a fragmentary cross-sectional view of the same portion as thatof FIG. 4 during a manufacturing step of the flash memory following thatof FIG. 4;

FIG. 6 is a fragmentary cross-sectional view of the same portion as thatof FIG. 4 during a manufacturing step of the flash memory following thatof FIG. 5;

FIG. 7 is a fragmentary cross-sectional view of the same portion as thatof FIG. 4 during a manufacturing step of the flash memory following thatof FIG. 6;

FIG. 8 is a fragmentary cross-sectional view of the same portion as thatof FIG. 4 during a manufacturing step of the flash memory following thatof FIG. 7;

FIG. 9 is a fragmentary cross-sectional view of the same portion as thatof FIG. 4 during a manufacturing step of the flash memory following thatof FIG. 8;

FIG. 10 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 9;

FIG. 11 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 10;

FIG. 12 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 11;

FIG. 13 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 12;

FIG. 14 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 13;

FIG. 15 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 14;

FIG. 16 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 15;

FIG. 17 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 16;

FIG. 18 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 17;

FIG. 19 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 18;

FIG. 20 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 19;

FIG. 21 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 20;

FIG. 22 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 21;

FIG. 23 is a fragmentary cross-sectional view of the same portion asthat of FIG. 4 during a manufacturing step of the flash memory followingthat of FIG. 22;

FIG. 24 is a fragmentary cross-sectional view of an AG-AND flash memoryaccording to Embodiment 2 of the present invention during itsmanufacturing step;

FIG. 25 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 24;

FIG. 26 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 25;

FIG. 27 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 26;

FIG. 28 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 27;

FIG. 29 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 28;

FIG. 30 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 29;

FIG. 31 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 30;

FIG. 32 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 31;

FIG. 33 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 32;

FIG. 34 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 33;

FIG. 35 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 34;

FIG. 36 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 35;

FIG. 37 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 36;

FIG. 38 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 37; and

FIG. 39 is a fragmentary cross-sectional view of the same portion asthat of FIG. 24 during a manufacturing step of the flash memoryfollowing that of FIG. 38.

DETAILED DESCRIPTION OF THE INVENTION

In the below-described embodiment, a description will be made afterdivided in plural sections or in plural embodiments if necessary forconvenience's sake. These plural sections or embodiments are notindependent each other, but in a relation such that one is amodification example, details or complementary description of a part orwhole of the other one unless otherwise specifically indicated.

In the below-described embodiments, when a reference is made to thenumber of elements (including the number, value, amount and range), thenumber is not limited to a specific number but can be greater than orless than the specific number unless otherwise specifically indicated orprincipally apparent that the number is limited to the specific number.Moreover in the below-described embodiments, it is needless to say thatthe constituting elements (including element steps) are not alwaysessential unless otherwise specifically indicated or principallyapparent that they are essential. Similarly, in the below-describedembodiments, when a reference is made to the shape or positionalrelationship of the constituting elements, that substantially analogousor similar to it is also embraced unless otherwise specificallyindicated or principally apparent that it is not. This also applies tothe above-described value and range.

In the drawings used in the embodiments, even a plain view sometimesincludes a shaded area to facilitate understanding of the drawings. Inthe embodiments, MIS-FET (Metal Insulator Semiconductor Field EffectTransistor) which is a typical example of field effect transistors isabbreviated as MIS, a p channel type MIS-FET is abbreviated as pMIS andan n channel type MIS-FET is abbreviated as nMIS.

In all the drawings for describing the embodiments, like members of afunction will be identified by like reference numerals and overlappingdescriptions will be omitted. The present invention will hereinafter bedescribed in detail based on accompanying drawings.

EMBODIMENT 1

In Embodiment 1, a description is made of one application example of theinvention to, for example, a monofunctional 4-Mbit AG-AND flash memory.FIG. 1 is a fragmentary plan view of a memory array (memory cell, assistgate binding portion and selecting nMIS formation region) of an AG-ANDflash memory according to Embodiment 1, FIG. 2 is a cross-sectional viewtaken along a line a-a of FIG. 1 and FIG. 3 is a cross-sectional viewtaken along a line b-b of FIG. 1.

A semiconductor substrate 1 of a semiconductor chip having a flashmemory of this Embodiment 1 formed thereover is made of, for example, ptype single crystal silicon. Over the main surface (device formationsurface) thereof, isolation portions 2, a plurality of assist gateelectrodes (first electrodes) 10 a, a plurality of word lines WL(control gate electrodes 16 (second electrodes)), a plurality offloating gate electrodes (third electrodes) 5 a, a plurality ofnonvolatile memory cells (which will hereinafter be called “memorycells” simply) MC and a plurality of selecting nMIS Qs0 and Qs1 areplaced. In the formation regions of the memory cell and selecting nMISof the semiconductor substrate 1, p well PW2 and buried n well NWm areformed, while the p well PW2 is, at the periphery thereof (side surfacesand bottom surface), encompassed by a buried n well NWm.

The isolation portions 2 each defines the planar profile of an activeregion in which the device is formed and it is regarded, for example, asa shallow trench isolation region called STI (Shallow Trench Isolation)or SGI (Shallow Groove Isolation). It is formed by filling an insulatingfilm such as silicon oxide in a shallow trench made in the semiconductorsubstrate 1.

The plurality of assist gate electrodes 10 a each has a rectangularplanar shape extending in a first direction X. The assist gateelectrodes 10 a are arranged in substantially parallel to each other ina second direction Y while maintaining a desired distance between anytwo of them. The size (width) of the assist gate electrode 10 a in thesecond direction Y is, for example, about 75 nm and the distance betweenthe two adjacent assist gate electrodes 10 a is, for example, about 105nm. The assist gate electrodes 10 a are placed so that most of themoverlap with the active region two-dimensionally. By the application ofa desired voltage to the assist gate electrodes 10 a, an n typeinversion layer is formed in the main surface portion of thesemiconductor substrate 1 in the active region along the assist gateelectrodes 10 a. This n type inversion layer is a portion forming a bitline (source and drain of memory cell MC). Accordingly, the activeregion has no semiconductor region constituting a bit line which isotherwise formed by the introduction of an impurity into thesemiconductor substrate 1. The assist gate electrodes 10 not onlyfunction to form the bit line but also have an isolation functionbetween two adjacent memory cells MC.

In a unit region of the memory cell, four assist gate electrodes 10 a(G0 to G3) are for example located. In other words, four assist gateelectrodes 10 a (G0 to G3) constitute one set. In FIG. 1, a wide-widthregion 10GA for connection to upper interconnects is formed on the rightend of an assist gate electrode 10 a (G1) of the unit region; awide-width region 10GA for connection to upper interconnects is formedon the left end of an assist gate electrode 10 a (G2) which lies belowand adjacent to the assist gate electrode 10 a (G1); the right end of anassist gate electrode 10 a (G3) which lies below and adjacent to theassist gate electrode 10 a (G2) is connected to an interconnect 10LA;and the left end of an assist gate electrode 10 a (G0) which lies belowand adjacent to the assist gate electrode 10 a (G3) is connected to aninterconnect 10LB. The interconnects 10LA and 10LB have a belt-likepattern extending in the second direction Y of FIG. 1 and assist gateelectrodes 10 a (G3, G0) are connected integrally to them, respectively.In other words, the interconnects 10LA and 10LB are interconnects commonto a plurality of assist gate electrodes 10 a for supplying the samepotential. Such assist gate electrodes 10 a, wide-width region 10GA andinterconnects 10LA and 10LB are formed by patterning a conductor filmmade of, for example, low resistance polycrystalline silicon in the samestep.

The assist gate electrodes 10 a are formed over the main surface of thesemiconductor substrate 1 via an insulating film (third insulating film)9 a of about 8 nm to 10 nm in thickness made of, for example, siliconoxide after dry etching to remove a damage layer by about 10 nm to 20nm. Over the side surfaces of each of all the assist gate electrodes 10a, an insulating film 7 made of, for example, silicon oxide andsidewalls 8 are formed. On the upper surface of the assist gateelectrodes 10 a, an insulating film (fourth insulating film) 11 made of,for example, silicon nitride is formed. In a portion of the width-wideregion 10GA and interconnects 10LA and 10LB, contact holes C1 areplaced. Via plugs in the contact holes C1, the assist gate electrodes 10are electrically connected to a first-level interconnect thereover.

The number of the plurality of word lines WL formed per memory cell(memory mat) of one block is 256. In this Embodiment 1, the word linesWL0 to WL2 are illustrated in order to facilitate understanding of them.Each word line WL has a rectangular planar shape extending in the seconddirection Y. Described specifically, word lines WL are arrangedsubstantially parallel to each other along the first direction X of FIG.1 at desired intervals while crossing the assist gate electrodes 10 a atright angles. A portion of the word line WL existing between twoadjacent assist gate electrodes 10 a is a control gate electrode 16 ofthe memory cell MC. The distance between two adjacent word lines WL is,for example, about 90 nm. The word lines WL are each composed of a filmstack obtained by stacking a conductor film 13 made of low resistancepolycrystalline silicon over a conductor film 14 made of a refractorymetal silicide. Over the upper surface of these word lines WL, a capinsulating film 15 made of, for example, silicon oxide is deposited. Asillustrated in FIG. 2, in the direction Y of each memory cell MC, theconductor film 13 constituting the lower layer of the word line WL isformed so as to fill between any two floating gate electrodes 5 a via aninterlayer film (fifth insulating film) 12.

The plurality of floating gate electrodes 5 a are arranged in anelectrically insulated state at intersections of a space between any twoadjacent assist gate electrodes 10 a with the word line WL. The floatinggate electrodes 5 a are each a charge accumulation layer for the data ofthe memory cell MC and is formed of, for example, low resistancepolycrystalline silicon. The floating gate electrodes 5 a are protrudedrelative to the surface of the semiconductor substrate 1 and have aprojecting cross-section (rectangular shape in this drawing) in thedirection crossing the main surface of the semiconductor substrate 1. Inother words, the floating gate electrodes 5 a have a columnar shape(quadrangular prism shape in this drawing) formed in regions sandwichedbetween the assist gate electrodes 10 a and their height (height fromthe main surface of the semiconductor substrate 1) is adjusted to behigher than the height (height from the main surface of thesemiconductor substrate 1) of the assist gate electrodes 10 a. The sizeof the floating gate electrodes 5 a in the first direction X is, forexample, about 90 nm, while that in the second direction Y is, forexample, about 65 nm.

The floating gate electrodes 5 a are placed over the main surface of thesemiconductor substrate 1 via an insulating film (first insulating film)4. This insulating film 4 functions as a tunnel insulating film of thememory cell MC and as will described later, it is made of silicon oxideformed, for example, by thermal oxidation such as ISSG (In-Situ SteamGeneration) oxidation over the main surface of the semiconductorsubstrate 1 which is clean and damage-free. The insulating film 4 has athickness of, for example, from about 8 nm to 10 nm. As described above,it is formed over the main surface of the semiconductor substrate 1 viathe insulating film 9 a after a damage layer removing step of, forexample, about 10 nm to 20 nm by dry etching. The floating gateelectrodes 5 a are formed over the main surface of the semiconductorsubstrate 1 via the insulating film 4 without such removal of the damagelayer so that as illustrated in FIG. 2, the lower surface of thefloating gate electrodes 5 a brought into contact with the insulatingfilm 4 is formed at a position higher than that of the lower surface ofthe assist gate electrodes 10 a brought into contact with the insulatingfilm 9 a.

Between the floating gate electrodes 5 a and the assist gate electrodes10 a are formed the insulating film 7 and sidewalls 8, by which thefloating gate electrodes 5 a are insulated from the assist gateelectrodes 10 a. Between two adjacent floating gates 5 a and twoadjacent word lines WL in the first direction X, an insulating film(sidewall 19) made of, for example, silicon oxide is formed and itinsulates between the floating gate electrodes 5 a and between wordlines WL which are adjacent to each other in the first direction X.

An interlayer film 12 is formed between the floating gate electrode 5 aand the control gate electrode 16 of the word line WL. The interlayerfilm 12 is a film for constituting a capacitor between the floating gateelectrode 5 a and the control gate electrode 16 and it is made of aso-called ONO film obtained by stacking a silicon oxide film, a siliconnitride film and a silicon oxide film one after another in the order ofmention. The interlayer film 12 has a thickness of, for example, about16 nm in terms of silicon dioxide (SiO₂) which is determined inconsideration of a dielectric constant.

The plurality of selecting nMIS Qs0 and Qs1 are placed on a bit lineside which will be a drain of the memory cell MC and on a bit line sidewhich will be its source, respectively. On the bit line side of FIG. 1which will be a drain, the selecting nMIS Qs0 are arranged along thesecond direction Y on the right side of FIG. 1 for each bit line. On thebit line side which will be a source, the selecting nMIS Qs1 arearranged along the second direction Y on the left side of FIG. 1 foreach bit line. A description will next be made of the nMIS Qs0 on thebit line side which will be a drain. The nMIS Qs1 on the bit line sidewhich will be a source has a structure similar to that of the nMIS Qs0so that a description will be omitted.

As illustrated in FIG. 1, a gate electrode of the selecting nMIS Qs0 onthe bit line side which will be a drain is formed in a portion (aportion of the active region crossing the belt-like region) of abelt-like interconnect 10LC extending in the second direction Y alongthe interconnect 10LA. A gate electrode of the selecting nMIS Qs1 on thebit line side which will be a source is formed in a portion (a portionof the active region crossing a belt-like region) of a belt-likeinterconnect 10LD extending in the second direction Y along theinterconnect 10LB. The gate electrodes, and interconnects 10LC and 10LDof the selecting nMIS Qs0 and 1 are each made of, for example, lowresistance polycrystalline silicon and are patterned simultaneously withthe patterning of the assist gate electrodes 10 a and wide-width region10GA and interconnects 10LA and 10LB. In portions of the interconnects10LC and 10LD, contact holes C1 are placed. Via plugs in the contactholes C1, the gate electrodes of the selecting nMIS Qs0 and Qs1 areelectrically connected to the first-level interconnect thereover.

One example of a manufacturing method of the AG-AND flash memoryaccording to this Embodiment 1 will next be described in the order ofsteps based on the fragmentary cross-sectional views of thesemiconductor substrate illustrated in FIGS. 4 to 23. These drawingsinclude memory cells (cross-sectional view taken along a line a-a ofFIG. 1 and parallel to word lines and cross-sectional view taken along aline b-b of FIG. 1 and perpendicular to word lines), assist gateelectrode binding portion (cross-sectional view taken along a line c-cof FIG. 1), selecting nMIS, peripheral circuit high breakdown voltageMIS, and peripheral circuit low breakdown voltage MIS.

As illustrated in FIG. 4, shallow trench type isolation portions 2, forexample, are formed in element isolation regions on the main surface ofa semiconductor substrate (in this stage, a semiconductor thin platehaving a substantially disc plane which is called “semiconductor wafer”)1 made of, for example, p type single crystal silicon. On an activeregion encompassed by the isolation portion 2 over the main surface ofthe semiconductor substrate 1, an insulating film 3 made of, forexample, silicon oxide is then formed by thermal oxidation. Thisinsulating film 3 has a function of protecting the semiconductorsubstrate 1 during ion implantation which will be described next.

Buried n-wells NWm are then formed by selectively introducing an n typeimpurity into the formation regions of the memory cell, assist gateelectrode binding portion and selecting nMIS in accordance with the ionimplantation method. In addition, a p well PW1 is formed in theformation region of the peripheral circuit high breakdown voltage nMIS,a p well PW2 is formed in the formation regions of the memory cell,assist gate electrode binding portion, selecting nMIS and peripheralcircuit low breakdown voltage nMIS, an n well NW1 is formed in theformation region of the peripheral circuit high breakdown voltage nMIS,and NW2 is formed in the formation region of the peripheral circuit lowbreakdown voltage pMIS by selectively introducing a predeterminedimpurity at a predetermined energy in accordance with the ionimplantation method.

As illustrated in FIG. 5, after removal of the insulating film 3, aninsulating film 4 of, for example, about 8 nm to 10 nm in thicknessserving as a tunnel insulating film (FTO film) of the memory cell isformed over the main surface of the semiconductor substrate 1, forexample, by ISSG (In-Situ Steam Generation) oxidation. The ISSGoxidation is one of thermal oxidation methods which directly introduceshydrogen and oxygen in a thermal treatment chamber and effects a radicaloxidation reaction over the heated semiconductor substrate 1. A siliconoxide film of about 8 nm in thickness can be formed over silicon, forexample, by adjusting a hydrogen concentration to 10% or greater in anatmosphere of 900° C. ISSG oxidation is characterized in that comparedwith thermal oxidation by the conventional RPT (Rapid Thermal Process),it can suppress speed-up diffusion of oxygen into the semiconductorsubstrate 1.

As illustrated in FIG. 6, a conductor film 5, for example, of about 250nm in thickness made of low resistance polycrystalline silicon isdeposited over the main surface of the semiconductor substrate 1 bythermal CVD (Chemical Vapor Deposition), followed by deposition of aninsulating film (second insulating film) made of silicon oxide andhaving a thickness of about 100 nm by CVD.

As illustrated in FIG. 7, with a resist pattern formed byphotolithography as a mask, the insulating film 6 and conductor film 5exposed therefrom are removed by dry etching. By this, the floating gateelectrodes 5 a of the memory cell made of the conductor film 5 arepatterned in the gate-width direction. The floating gate electrodes 5 aeach has a width of about 90 nm.

The floating gate electrodes 5 a are disposed over the main surface ofthe semiconductor substrate 1 via the insulating film 4 serving as atunnel insulating film of the memory cell. This insulating film 4 isformed over the main surface of the semiconductor substrate 1 which isclean and damage free, for example, by the ISSG oxidation and it has theconductor film 5 deposited thereover by thermal CVD which causes lessdamage so that high reliability can be imparted to the tunnel insulatingfilm.

As illustrated in FIG. 8, the semiconductor substrate 1 is subjected tothermal oxidation treatment to form an insulating film 7 made of siliconoxide over the side surfaces of each of the floating gate electrodes 5a. By this thermal oxidation treatment, the floating gate electrodes 5 ahave a width of about 80 nm. After deposition of an insulating film madeof, for example, silicon oxide over the main surface of thesemiconductor substrate by CVD, the resulting insulating film is etchedback by anisotropic dry etching, whereby sidewalls 8 are formed over theside surfaces of each of the floating gate electrode 5 a and insulatingfilm 6. The total thickness of the insulating film 7 and sidewalls 8 isabout 20 nm. During the formation of the sidewalls 8, a damage layersuch as dislocation or crystal defects appears in single crystal siliconconstituting the semiconductor substrate 1. The damage layer istherefore removed by etching a 10 nm to 20 nm portion from the surfaceof the semiconductor substrate 1, for example, by dry etching. Removalof the damage layer in such a manner enables removal of defects betweenthe assist gate insulating film 9 a which will be formed in thesubsequent step and semiconductor substrate 1.

As illustrated in FIG. 9, the insulating film 9 a of about 9 nm inthickness and an insulating film 9 b of about 25 nm in thickness areformed over the main surface of the semiconductor substrate 1, forexample, by ISSG oxidation. The insulating film 9 a constitutes, forexample, an assist gate insulating film of the memory cell and gateinsulating films of the selecting nMIS and peripheral circuit lowbreakdown voltage nMIS and pMIS, while the insulating film 9 bconstitutes gate insulating films of the peripheral circuit highbreakdown voltage nMIS and pMIS.

These insulating films 9 a and 9 b are formed, for example, in thefollowing manner. First, the semiconductor substrate 1 is subjected tothermal oxidation treatment using, for example, ISSG oxidation to forman insulating film (the sixth insulating film) made of silicon oxide andhaving, for example, a thickness of about 20 nm over the main surface ofthe semiconductor substrate. This thermal oxidation treatment maypresumably form a bird's beak at the end portions of the insulating film4 which has already been formed over the main surface of thesemiconductor substrate 1. Use of ISSG oxidation method, however,suppresses the formation of the bird's beak. With a resist patternformed by photolithography as a mask, the insulating film made ofsilicon oxide is removed by wet etching or dry etching from theformation regions of the memory array and peripheral circuit lowbreakdown voltage nMIS and pMIS. By the thermal oxidation treatment ofthe semiconductor substrate 1, an insulating film 9 a made of siliconoxide is formed over the main surface of the semiconductor substrate 1in the formation regions of the memory array and peripheral circuit lowbreakdown voltage nMIS and pMIS, while an insulating film 9 b made ofsilicon oxide, for example, is formed over the main surface of thesemiconductor substrate 1 in the formation regions of the peripheralcircuit high breakdown voltage nMIS and pMIS. The insulating film 9 a tobe formed in the formation region of the memory cell functions as anassist gate insulating film.

As illustrated in FIG. 10, a conductor film 10 made of low resistancepolycrystalline silicon and having a thickness of from about 90 nm to100 nm is deposited over the main surface of the semiconductor substrate1. Since the distance between the two adjacent floating gate electrodes5 a is, for example, about 90 nm so that the conductor film 10 is filledbetween the two adjacent floating gate electrodes 5 a.

As illustrated in FIG. 11, with a resist pattern formed byphotolithography as a mask, an unnecessary portion of the conductor film10 exposed therefrom is removed by wet etching, whereby the assist gateelectrodes 10 a of the memory cell made of the conductor film 10 arepatterned in the gate-width direction.

As illustrated in FIG. 12, an insulating film 11 made of silicon nitrideand having a thickness of from 90 nm to 100 nm is deposited over themain surface of the semiconductor substrate 1. The distance between thetwo adjacent floating gate electrodes 5 a is, for example, about 90 nmso that the insulating film 11 is filled between the two adjacentfloating gate electrodes 5 a.

As illustrated in FIG. 13, with a resist pattern formed byphotolithography as a mask, an unnecessary portion of the insulatingfilm 11 is removed by wet etching, whereby the insulating film 11 can beleft over the assist gate electrodes 10 a of the memory cell and theconductor film 10 in the formation regions of the selecting nMIS andperipheral circuit.

As illustrated in FIG. 14, the insulating film 6 over the floating gateelectrodes 5 a is selectively removed by dry etching.

As illustrated in FIG. 15, the exposed side walls 8 which are formedover the side surfaces of the floating gate electrode 5 a are removed bywet etching, followed by removal of the insulating film 7 which isexposed by the removal of the sidewalls 8 by wet etching.

As illustrated in FIG. 16, an interlayer film 12 is formed bydepositing, in the order of mention, a silicon oxide film, a siliconnitride film and a silicon oxide film over the main surface of thesemiconductor substrate 1 by CVD.

As illustrated in FIG. 17, a conductor film 13 made of low resistancepolycrystalline silicon and having, for example, a thickness of about150 nm, a conductor film 14 which has lower resistance than theconductor film 13 and having, for example, a film thickness of about 40nm, and a cap insulating film 15 made of silicon oxide or the like aredeposited over the main surface of the semiconductor substrate 1 in theorder of mention by CVD. As the conductor film 14, a refractory metalsilicide film such as tungsten silicide is employed.

As illustrated in FIG. 18, with a resist pattern formed byphotolithography as a mask, the cap insulating film 15 and conductorfilms 13 and 14 exposed from the mask are removed by dry etching,whereby control gate electrodes 16 of the memory cell made of theconductor films 13 and 14 are formed.

As illustrated in FIG. 19, with a resist pattern formed byphotolithography and remaining cap insulating film 15 as masks, theinterlayer film 12 and conductor film 5 exposed therefrom are removed bydry etching, whereby the floating gate electrode 5 a of the memory cellis patterned in the gate length direction. As a result, the control gateelectrode 16 and floating gate electrode 5 a of the memory cell arecompleted.

As illustrated in FIG. 20, with a resist pattern formed byphotolithography as a mask, the interlayer film 12, insulating film 11and conductor film 10 of the peripheral circuit exposed from the maskare removed by dry etching, whereby gate electrodes 10 b of theselecting nMIS, peripheral circuit high breakdown voltage nMIS and pMIS,and peripheral circuit low breakdown voltage nMIS and pMIS are formed.

A pair of n type semiconductor regions 17 having a relatively lowimpurity concentration which regions constitute a portion of the sourceand drain for the selecting nMIS and peripheral circuit high breakdownvoltage and low breakdown voltage nMISs are then formed. Into the n typesemiconductor regions 17, ions such as arsenic or phosphorus areimplanted. A pair of p type semiconductor regions 18 having a relativelylow impurity concentration which regions constitute a portion of thesource and drain for the peripheral circuit high breakdown voltage andlow breakdown voltage pMISs are then formed. Into the p typesemiconductor regions 18, ions such as boron or boron fluoride areimplanted.

As illustrated in FIG. 21, after deposition of an insulating film madeof, for example, silicon oxide over the main surface of thesemiconductor substrate 1 by CVD, the insulating film is etched back byanisotropic dry etching to form side walls over the side surfaces ofeach of the gate electrodes 10 b of the selecting nMIS, peripheralcircuit high breakdown voltage nMIS and pMIS and peripheral circuit lowbreakdown voltage nMIS and pMIS. During the formation, the insulatingfilm constituting the sidewalls 19 is also filled between the twoadjacent floating gate electrodes 5 a and between the two adjacentcontrol gate electrodes 16 and it thus insulates between the floatinggate electrodes 5 a and control gate electrodes 16.

A pair of n type semiconductor regions 20 having a relatively highimpurity concentration which regions constitute another portion of thesource and drain of the selecting nMIS and peripheral circuit highbreakdown voltage and low breakdown voltage nMISs and are then formed.In the n type semiconductor regions, arsenic ions, for example, areimplanted. A pair of p type semiconductor regions 21 having a relativelyhigh impurity concentration which regions constitute a portion of thesource and drain of the peripheral circuit high breakdown voltage andlow breakdown voltage pMISs are then formed. Into the p typesemiconductor regions 21, boron for example, are ion implanted. In orderto activate these impurities thus ion implanted, the semiconductorsubstrate 1 is subjected to thermal treatment of about 900° C. to 1000°C. By the above-described steps, various MISs of the memory array andperipheral circuit are formed.

As illustrated in FIG. 22, an insulating film 22 made of, for example,silicon oxide is deposited over the main surface of the semiconductorsubstrate 1 by CVD. With a resist pattern formed by photolithography asa mask, the insulating film 22 exposed therefrom is removed by dryetching to form contact holes C1 from which portions (for example,memory cell and source and drain of various MISs) of the semiconductorsubstrate 1 and a portion of the word lines WL are exposed.

After deposition of, for example, a titanium film, a titanium nitridefilm and a tungsten film over the main surface of the semiconductorsubstrate 1 in the order of mention by sputtering or CVD, these metalfilms are polished by CMP to leave them only inside of the contact holeC1, whereby a plug 23 is formed inside of the contact hole C1. Over themain surface of the semiconductor substrate 1, an aluminum alloy filmand a titanium nitride film, for example, are deposited in the order ofmention by sputtering. With a resist pattern formed by photolithographyas a mask, the titanium nitride film and aluminum alloy film exposedtherefrom are removed by dry etching to form a first-level interconnectM1.

As illustrated in FIG. 23, an insulating film 24 made of, for example,silicon oxide is deposited by CVD over the main surface of thesemiconductor substrate 1. With a resist pattern formed byphotolithography as a mask, the insulating film 24 exposed therefrom isremoved by dry etching, whereby a through-hole T1 from which a portionof the first-level interconnect M1 is exposed is formed in theinsulating film 24.

After deposition of, for example, a titanium film, a titanium nitridefilm and a tungsten film over the main surface of the semiconductorsubstrate 1 in the order of mention by sputtering or CVD, these metalfilms are polished by CMP to leave them only inside of the contact holeT1, whereby a plug 25 is formed inside of the contact hole T1. Over themain surface of the semiconductor substrate 1, an aluminum alloy filmand a titanium nitride film, for example, are deposited in the order ofmention by sputtering. With a resist pattern formed by photolithographyas a mask, the titanium nitride film and aluminum alloy film exposedtherefrom were removed by dry etching to form a second-levelinterconnect M2. The second-level interconnect M2 is electricallyconnected to the first-level interconnect M1 via the plug 25.

After deposition of an insulating film 26 made of, for example, siliconoxide over the main surface of the semiconductor substrate 1 by CVD, athrough-hole T2 from which a portion of the second-level interconnect M2is exposed is formed in the insulating film 26 in a similar manner tothat employed for the formation of the through-hole T1. A plug 27 isformed inside of the through-hole T2 in a similar manner to thatemployed for the formation of the plug 25 and second-level interconnectM2. In such a manner, a third-level interconnect M3 electricallyconnected to the second-level interconnect M2 via the plug 27 is formed.

Upper-level interconnects are thereafter formed. The surface of theuppermost-level interconnect is covered with a surface protection film.An opening portion from which a portion of the upper-most levelinterconnect is exposed is formed and a bonding pad is formed, whereby aflash memory is manufactured.

According to Embodiment 1, a tunnel insulating film of a memory cellhaving high reliability can be obtained by forming the insulating film 4serving as a tunnel insulating film of a memory cell over the mainsurface of the semiconductor substrate 1 which is clean and damage free,forming the floating gate electrode 5 a and then forming the assist gateelectrode 10 a. This enables formation of a memory cell with highreliability.

EMBODIMENT 2

One example of a manufacturing method of an AG-AND flash memoryaccording to Embodiment 2 will next be described in the order of stepsbased on the fragmentary cross-sectional views of a semiconductorsubstrate in FIGS. 24 to 39. What is different from the above-describedEmbodiment 1 is that an insulating film functioning as a tunnelinsulating film of a memory cell and a gate insulating film ofperipheral circuit low breakdown voltage nMIS and pMIS are formed as thesame layer and a floating gate electrode of a memory cell and gateelectrodes of various MISs of a peripheral circuit are formed as thesame layer.

As in the above-described Embodiment 1, an isolation portion 2 and anactive region encompassed therewith are formed over the main surface ofa semiconductor substrate 1. Then, a buried n well NWm, p wells PW1 andPW2, and n wells NW1 and NW2 are formed in predetermined portions of thesemiconductor substrate 1.

As illustrated in FIG. 24, an insulating film 50 a of about 8 nm to 10nm in thickness and an insulating film 50 b of about 25 nm in thicknessare formed over the main surface of the semiconductor substrate 1. Theinsulating film 50 a serves, for example, as a tunnel insulating film ofa memory cell and moreover, constitutes a gate insulating film of aselecting nMIS, and peripheral circuit low breakdown voltage nMIS andpMIS. The insulating film 50 b constitutes, for example, peripheralcircuit high breakdown voltage nMIS and pMIS. These insulating films 50a and 50 b are formed using, for example, ISSG oxidation in a similarstep to that employed for the formation of the insulating films 9 a and9 b as described in Embodiment 1.

After deposition of a conductor film 5 of, for example, about 250 nm inthickness made of low resistance polycrystalline silicon over the mainsurface of the semiconductor substrate 1, an insulating film 6 of, forexample, about 100 nm in thickness made of silicon oxide is depositedover the conductor film 5 by CVD (Chemical Vapor Deposition).

As illustrated in FIG. 25, with a resist pattern formed byphotolithography as a mask, the insulating film 6 and conductor film 5exposed therefrom are removed by dry etching, whereby floating gateelectrodes 5 a of the memory cell made of the conductor film 5 arepatterned in a gate width direction. At the same time, unnecessaryportions of the insulating film 6 and conductor film 5 are removed fromthe assist gate electrode binding portion while leaving the conductorfilm and insulating film 6 in the selecting nMIS and peripheral circuitformation regions.

As in the above-described Embodiment 1, the floating gate electrodes 5 aare disposed over the main surface of the semiconductor substrate 1 viathe insulating film 50 a functioning as a tunnel insulating film of thememory cell. This insulating film 50 a is formed over the main surfaceof the semiconductor substrate 1 which is clean and damage-free, forexample, by ISSG oxidation and the conductor film 5 is deposited overthe insulating film 50 a by thermal CVD which causes less damage so thata tunnel insulating film with high reliability can be obtained.

In the flash memory, the gate insulating films of the peripheral circuithigh breakdown voltage nMIS and pMIS are required to have highreliability next to that of the memory cell, because the peripheralcircuit high breakdown voltage nMIS and pMIS are used mainly for acircuit having a relatively long operation time such as power supplycircuit or a decoder circuit and a stress is therefore applied to thegate insulating film for long hours. In Embodiment 2, however, sincegate insulating films of the high breakdown voltage nMIS and pMIS aremade of the insulating film 50 b formed over the main surface of thesemiconductor substrate 1 which is clean and damage free, a gateinsulating film with high reliability is available. The insulating film50 a also constitutes the gate insulating films of the peripheralcircuit low breakdown voltage nMIS and pMIS used mainly for a logiccircuit so that a similar advantage can be obtained.

As illustrated in FIG. 26, the semiconductor substrate 1 is subjected tothermal oxidation treatment to form an insulating film 7 made of siliconoxide over the side surfaces of the floating gate electrode 5 a. Then,sidewalls 8 are formed over the side surfaces of the floating gateelectrode 5 a and insulating film 6. During the formation of thesidewalls 8, a damage layer such as dislocation or crystal defects isformed in single crystal silicon constituting the semiconductorsubstrate 1. The surface of the semiconductor substrate 1 is thereforeetched by about 10 nm by, for example, dry etching to remove the damagelayer. Since the damage layer is thus removed in advance, defectsbetween an assist gate insulating film 9 a which will be formed laterand semiconductor substrate 1 can be removed.

As illustrated in FIG. 27, an insulating film 51 of from about 8 nm to10 nm in thickness which constitutes an assist gate insulating film ofthe memory cell is formed over the main surface of the semiconductorsubstrate 1 by thermal oxidation.

As illustrated in FIG. 28, a conductor film 10 of, for example, fromabout 90 nm to 100 nm in thickness made of low resistancepolycrystalline silicon is deposited over the main surface of thesemiconductor substrate 1. Since the distance between two adjacentfloating gate electrodes 5 a is, for example, about 90 nm, the spacebetween the two adjacent floating gate electrodes 5 a can be filled withthe conductor film 10.

As illustrated in FIG. 29, an unnecessary portion of the conductor film10 is removed by dry etching, whereby the assist gate electrodes 10 a ofthe memory cell made of the conductor film 10 are patterned in the gatewidth direction.

As illustrated in FIG. 30, an insulating film 11 of, for example, fromabout 90 nm to 100 nm in thickness made of silicon nitride is depositedover the main surface of the semiconductor substrate 1. Since thedistance between two adjacent floating gate electrodes 5 a is, forexample, about 90 nm, the space between the two adjacent floating gateelectrodes 5 a can be filled with the insulating film 11.

As illustrated in FIG. 31, the insulating film 11 is etched back by dryetching until the exposure of the insulating film 6. The insulating film11 is filled between the two adjacent assist gate electrodes 10 a of thememory cell and the surface of the insulating film 11 is thenplanarized.

As illustrated in FIG. 32, with a resist pattern formed byphotolithography as a mask, the insulating film 11 and conductor film 10exposed therefrom and existing at the end portions of the assist gateelectrode binding portion are removed by dry etching.

As illustrated in FIG. 33, with a resist pattern formed byphotolithography as a mask, an unnecessary portion of the insulatingfilm 11 exposed therefrom is removed by wet etching, whereby theinsulating film 11 of for example, about 80 nm in thickness can be leftover the assist gate electrodes 10 a of the memory cell.

As illustrated in FIG. 34, the insulating film 6 over the floating gateelectrode 5 a is selectively removed by dry etching.

As illustrated in FIG. 35, the exposed sidewalls 8 formed over the sidesurface of the floating gate electrodes 5 a are removed by wet etching,followed by wet etching to remove the insulating film 7 exposed by theremoval of the sidewalls 8.

As illustrated in FIG. 36, an interlayer film 12 is formed bydepositing, for example, a silicon oxide film, a silicon nitride filmand a silicon oxide film in the order of mention over the main surfaceof the semiconductor substrate 1 by CVD. Then over the main surface ofthe semiconductor substrate 1, a conductor film 13 of, for example,about 150 nm in thickness made of low resistance polycrystalline, aconductor film 14 of, for example, about 40 nm in thickness made of arefractory metal silicide and a cap insulating film 15 made of siliconoxide or the like are deposited in the order of mention by CVD.

As illustrated in FIG. 37, with a resist pattern formed byphotolithography as a mask, the cap insulating film 15 and conductorfilms 13 and 14 exposed therefrom are removed by dry etching, wherebycontrol gate electrodes 16 of the memory cell each made of the conductorfilms 13 and 14 are formed.

With a resist pattern formed by photolithography and the remaining capinsulating film 15 as masks, the interlayer film 12 and conductor film 5exposed therefrom are removed by dry etching, whereby the floating gateelectrodes 5 a of the memory cell are patterned in the gate lengthdirection. As a result, the control gate electrode 16 and floating gateelectrodes 5 a of the memory cell are completed.

As illustrated in FIG. 38, with a resist pattern formed byphotolithography as a mask, the interlayer film 12, insulating film 6and conductor film 5 of the peripheral circuit exposed from the mask areremoved by dry etching, whereby the gate electrodes 5 b of the selectingnMIS, peripheral circuit high breakdown voltage nMIS and pMIS andperipheral circuit low breakdown voltage nMIS and pMIS are formed.

Next, a pair of n type semiconductor regions 17 having a relatively lowimpurity concentration and constituting a portion of the source anddrain of each of the selecting nMIS, and peripheral circuit highbreakdown voltage and low breakdown voltage nMISs and a pair of p typesemiconductor regions 18 having a relatively low impurity concentrationand constituting a portion of the source and drain of each of theperipheral circuit high breakdown voltage and low breakdown voltagepMISs are formed.

As illustrated in FIG. 39, sidewalls 19 are formed over the sidesurfaces of the gate electrodes 5 b of each of the selecting nMIS,peripheral circuit high breakdown voltage nMIS and pMIS and peripheralcircuit low breakdown voltage nMIS and pMIS. Then, a pair of n typesemiconductor regions 20 having a relatively high impurity concentrationand constituting the other portion of the source and drain of each ofthe selecting nMIS, and peripheral circuit high breakdown voltage andlow breakdown voltage nMISs and a pair of p type semiconductor regions21 having a relatively high impurity concentration and constituting theother portion of the source and drain of each of the peripheral circuithigh breakdown voltage and low breakdown voltage pMISs are formed. Inorder to activate the impurity ions thus implanted, the semiconductorsubstrate 1 is heat treated at a temperature, for example, from about900° C. to 1000° C. By the above-described steps, various MISs of thememory array and peripheral circuit are formed.

A flash memory as illustrated in FIG. 18 is manufactured by thefollowing steps performed as in the above-described Embodiment 1 so thatthe description on them is omitted.

According to Embodiment 2, advantages similar to those obtained in theabove-described Embodiment 1 can be obtained. In addition, since theinsulating film 50 b functioning as a gate insulating film of theperipheral circuit high breakdown voltage nMIS and pMIS is formed overthe main surface of the semiconductor substrate 1 which is clean anddamage-free, a highly-reliable gate insulating film of the highbreakdown voltage nMIS and pMIS can be obtained. This makes it possibleto form the high breakdown voltage nMIS and pMIs with high reliabilityin the peripheral circuit.

The inventions made by the present inventors were described specificallybased on some embodiments. It is however needless to say that thepresent invention is not limited to them but can be changed within arange not departing from the scope of the present invention.

The inventions made by the present inventors were applied to asemiconductor device composed only of an AND flash memory which belongsto the industrial field becoming the background of the invention, butthey are applied not only to it but also a semiconductor device havingcomposed only of an EEPROM, and memory-embedded semiconductor devicesuch as system LSI (Large Scale Integrated Circuit) having EEPROM orflash memory.

The semiconductor device of the present invention can be applied tosemiconductor devices having a nonvolatile semiconductor memory such asEEPROM or flash memory.

1. A manufacturing method of a semiconductor device equipped with a plurality of nonvolatile memory cells each comprising a plurality of first electrodes placed over a semiconductor substrate, a plurality of second electrodes disposed over the semiconductor substrate to cross the plurality of first electrodes, and a plurality of third electrodes for charge accumulation disposed at positions which lie between any two adjacent ones of the plurality of first electrodes and overlap with the plurality of second electrodes two-dimensionally, the method comprising the steps of: (a) forming a first insulating film over the semiconductor substrate wherein said first insulating film has silicon oxide as a main component thereof; (b) depositing, over the first insulating film, a third-electrode forming conductor film having polycrystalline silicon as a main component thereof; (c) depositing a second insulating film over the third-electrode forming conductor film; (d) patterning the second insulating film and the third-electrode forming conductor film to form a plurality of layered patterns having the second insulating film and the third-electrode forming conductor film; (e) forming sidewalls over the side surfaces of each of the plurality of layered patterns; (f) forming a third insulating film over the semiconductor substrate between any two adjacent ones of the plurality of layered patterns; (g) depositing over the semiconductor substrate a first-electrode forming conductor film to fill the film between any two adjacent ones of the plurality of layered patterns; (h) removing the first-electrode forming conductor film to leave the film between any two adjacent ones of the plurality of layered patterns, thereby forming the plurality of first electrodes between any two adjacent ones of the plurality of layered patterns in self alignment with the plurality of layered patterns; (i) depositing a fourth insulating film over the semiconductor substrate to fill the film between any two adjacent ones of the plurality of layered patterns; (j) removing the fourth insulating film to leave a portion of the fourth insulating film between any two adjacent ones of the plurality of layered patterns, thereby forming the pattern of the fourth insulating film over the plurality of first electrodes between any two adjacent ones of the plurality of layered patterns in self alignment with the plurality of layered patterns; (k) removing the second insulating film; (l) removing the exposed sidewalls; (m) depositing a fifth insulating film over the semiconductor substrate; (n) depositing a second-electrode forming conductor film over the fifth insulating film; (o) patterning the second-electrode forming conductor film to form the plurality of second electrodes; and (p) patterning the third-electrode forming conductor film with the plurality of second electrodes as a mask, thereby forming the plurality of third electrodes having a projecting cross-section permitting the plurality of third electrodes to be higher than the plurality of first electrodes in self alignment with the plurality of second electrodes.
 2. A manufacturing method of a semiconductor device according to claim 1, further comprising a step of: (q) after the step (e), etching the semiconductor substrate between any two adjacent ones of the plurality of layered patterns by from about 10 nm to 20 nm.
 3. A manufacturing method of a semiconductor device according to claim 1, wherein the second insulating film has silicon oxide as a main component and the fourth insulating film has silicon nitride as a main component.
 4. A manufacturing method of a semiconductor device according to claim 1, wherein the plurality of third electrodes have a columnar shape.
 5. A manufacturing method of a semiconductor device according to claim 1, wherein the plurality of first electrodes have a function of forming an inversion layer over the semiconductor substrate. 